Therefore the smallest LUT in my design is going to be a LUT3 built with one 74HC595 and another 74HC151 as a 8:1 multiplexer. The LUT essentially consists of this memory and a big multiplexer selecting (looking up) the correct bit in the memory (table) for a given input.Īgain 16:1 multiplexer do not seem to be such a common IC type. There do not seem many alternatives which would offer 16 bits in a single chip so the 595 it is. It uses a straight forward SPI interface where the bitstream is shifted in and remains there for as long as the chip is powered on. Early on I knew that the LUT would be built using the good ol’ 74HC595 8 bit shift register. Regular preselect input from CBh instance INMODE_PRESELįig 2: Input post seletion multiplexer for a single LUT instance. This post selection process can be configured to pick any of the following input options: insel_* To support an input of two 4 bit input vectors, I added a post-selection multiplexers for input bits of each LUT. They can be tied to GND for the arithmetic mode. The first two inputs bits are shared to be the same between all 4 LUTs of a slice. Instead of 4 input multiplexers to supply all 4 input bits of all 4 LUTs at the same time, each input bit of each LUT would have its own multiplexer. This method comes at the cost of a much more complex input selection circuit. If the LUTs were independent, with independent inputs, there is much greater flexibility to loop the signal back into another LUT of the same CLB to apply another register stage onto a single bit. Here, you would have one input bit and tie all the remaining ones to ground, making it necessary to use two entire CLB slices to synchronize a single bit with two flip flops. Having the same input vector for all LUTs inside a CLB would be wasteful for any single bit functions and would make arithmetic operations on two 4 bit numbers impossible in a single CLB slice.Īn example for a single bit application is something that primarily makes use of the register stage after the LUT - say a debounce circuit or a double flip flop stage for clock domain crossing. all output bits would have the same input bit vector.

potentially having to deal with kbits of unused data still in the bitstream.resize the memory to something a lot smaller (e.g.Since all SRAM of today consist of several kbit of memory and therefore fairly large address and data I/O busses this would be a waste of resources and complexits: My very first idea of how a CLB could be implemented was to take a single SRAM chip with parallel address input and data I/Os. I will just call my group of LUTs a configurable logic slice ( CLB).

Terminology for the modular parts inside the FPGA fabric differ from manufacturer to manufacturer. The heart of any fully programmable digital logic part: the look up table - or more broadly speaking, a group of look up tables in a slice. Today, my fellow FPGA nerd, I proudly present to you the first module of the shittiest FPGA project.

Look up tables in fpga